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ksz8051mnlu/ksz8051rnlu 10base - t/100base - tx physical layer transceiver data sheet rev. 1.0 linkmd is a registered trademark of micrel, inc. micrel inc. ? 2180 fortune drive ? san jose, ca 95131 ? usa ? tel +1 ( 408 ) 944 - 0800 ? fax + 1 (408) 474 - 1000 ? http://www.micrel.com february, 1 7 2013 revision 1 .0 general description the ksz 8051 is a n aec - q100 standard qualified single - supply 10base - t/100base - tx ethernet physical - layer transceiver for transmission and reception of data over standard cat - 5 unshielded twisted pair (utp) cable for automotive applicatio ns . the ksz 8051 is a highly - integrated phy solution. it reduces board cost and simplifies board layout by using on - chip termination resistors for the differential pairs and by integrating a low - noise regulator to supply the 1.2v core . the ksz 8051mnlu offer s the media independent interface (mii) and the ksz 8051rnlu offers the reduced media independent interface (rmii) for direct connection with mii /rmii - compliant ethernet mac processors and switches. a 25mhz crystal is used to generate all required clocks, i ncluding the 50mhz rmii reference clock output for the ksz 8051rnlu . the ksz 8051 provides diagnostic features to facilitate system bring - up and debugging in production testing and in product deployment. parametric nand tree support enables fault detection between ksz 8051 i/os and the board. micrel linkmd ? tdr - based cable diagnostics identify faulty copper cabling. the ksz 8051mnlu and ksz 8051rnlu are available in 32 - pin, lead - free qfn packages (see ordering information ). d ata sheets and support documentation are available on micrels web site at: www.micrel.com . features ? single - chip 10base - t/100base - tx ieee 802.3 compliant ethernet t ransceiver ? aec - q100 qualified for automotive applica tions ? mii i nterface support (ksz 8051mnlu ) ? rmii v1.2 interface support with a 50mhz reference clock output to mac, and an option to input a 50mhz reference clock (ksz 8051rnlu ) ? back - to -b ack mode support for a 100mbps copper repeater ? mdc/mdio management i nter face for phy register configuration ? programmable interrupt output ? led outputs for link, activity , and speed status indication ? on - chip termination resistors for the differential pairs ? baseline wander c orrection ? hp auto mdi/mdi - x to reliably detect and corre ct straight - through and crossover cable connections with disable and enable option ? auto - negotiation to automatically select the highest link - up speed (10/100mbps) and duplex (half/full) ? power - down and power - saving modes ? linkmd tdr - based cable diagnostics t o identif y faulty copper cabling ? parametric nand tree support for fault detect ion between chip i/os and the board functional diagram downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 2 revision 1.0 features (continued) ? loopback modes for diagnostics ? single 3.3v power supply with vdd i/o options for 1.8v, 2.5v, or 3.3v ? built - in 1.2v regulator for core ? 32 - pin (5mm x 5mm) qfn package applications ? automotive (throughout vehicle) ordering information part number temperature range package lead finish wire bonding description ksz8051mnlu (1) ? 40c to 85 c 32 - pin qfn pb-free mii, automotive qualified device ksz8051rnlu (1) ? 40c to 85 c 32 - pin qfn pb-free rmii, automotive qualified device note: 1. contact factory for lead time. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 3 revision 1.0 revision history revision date summary of changes 0.1 7/6/12 initial release 0.2 7/9/12 added aec - q100 qualified to general description and features on page 1. 1.0 2/1 7 /1 3 general u pgrade to align to ksz8081 ds. loopback details added. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 4 revision 1.0 contents general description ................................................................................................................................................................ 1 features .................................................................................................................................................................................. 1 functional diagram ................................................................................................................................................................ . 1 features (continued) .............................................................................................................................................................. 2 applications ............................................................................................................................................................................. 2 ordering information ............................................................................................................................................................... 2 revision history ...................................................................................................................................................................... 3 contents .................................................................................................................................................................................. 4 list of figures .......................................................................................................................................................................... 6 list of tables ........................................................................................................................................................................... 7 pin configuration C ksz8051mnlu ........................................................................................................................................ 8 pin description C ksz8051mnlu ............................................................................................................................................ 9 strapping options C ksz8051mnlu .................................................................................................................................... 12 pin configuration C ksz8051rnlu ...................................................................................................................................... 13 pin des cription C ksz8051rnlu .......................................................................................................................................... 14 strapping options C ksz8051rnlu .................................................................................................................................... 17 functional description: 10base - t/100base - tx transceiver ................................................................................................ 18 100base - tx transmit .......................................................................................................................................................................... 18 100base - tx receive ........................................................................................................................................................................... 18 scrambler/de- scrambler (100b ase - tx only) ...................................................................................................................................... 18 10base - t transmit .............................................................................................................................................................................. 18 10base - t receive ............................................................................................................................................................................... 19 sqe and jabber function (10base - t only) ........................................................................................................................................ 19 pll clock synthesizer ........................................................................................................................................................................ 19 auto- negotiation .................................................................................................................................................................................. 19 mii interface (ksz8051mnlu only) ...................................................................................................................................... 20 mii signal definition ............................................................................................................................................................................. 20 mii signal diagram .............................................................................................................................................................................. 22 rmii data interface (ksz8051rnlu only) ........................................................................................................................... 23 rmii C 25mhz clock mode .................................................................................................................................................................. 23 rmii C 50mhz clock mode .................................................................................................................................................................. 23 rmii signal definition .......................................................................................................................................................................... 23 rmii signal diagram ........................................................................................................................................................................... 25 back - to - bac k mode C 100mbps copper repeater ............................................................................................................... 26 mii back - to - back mode (ksz8051mnlu only) ................................................................................................................................... 26 rmii back - to - back mode (ksz8051rnlu only) ................................................................................................................................ . 27 mii management (miim) interface ......................................................................................................................................... 27 interrupt (intrp) ................................................................................................................................................................... 28 hp auto mdi /mdi -x .............................................................................................................................................................. 28 straight cable ...................................................................................................................................................................................... 28 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 5 revision 1.0 crossover cable .................................................................................................................................................................................. 29 loopback mode ..................................................................................................................................................................... 30 local (digital) loopback ...................................................................................................................................................................... 30 remote (analog) loopback ................................................................................................................................................................ . 30 linkmd ? cable diagnostic .................................................................................................................................................... 31 nand tree support .............................................................................................................................................................. 31 nand tree i/o testing ....................................................................................................................................................................... 33 power management .............................................................................................................................................................. 34 power - saving mode ............................................................................................................................................................................ 34 energy - detect power - down mode ...................................................................................................................................................... 34 power - down mode .............................................................................................................................................................................. 34 slow- oscillator mode ........................................................................................................................................................................... 34 reference circuit for power and ground connections ......................................................................................................... 35 typical current/power consumption .................................................................................................................................... 36 transceiver (3.3v), digital i/os (3.3v) ................................................................................................................................................. 36 tra nsceiver (3.3v), digital i/os (2.5v) ................................................................................................................................................. 36 transceiver (3.3v), digital i/os (1.8v) ................................................................................................................................................. 37 register map ......................................................................................................................................................................... 38 register description .............................................................................................................................................................. 39 absolute maximum ratings (1) ................................................................................................................................................ 48 operating ratings (2) .............................................................................................................................................................. 48 electrical characteristics (3) .................................................................................................................................................... 48 timing diagrams ................................................................................................................................................................... 50 mii sqe timing (10base - t) ................................................................................................................................................................ 50 mii transmit timing (10base - t) .......................................................................................................................................................... 51 mii receive timing (10base - t) ........................................................................................................................................................... 52 mii transmit timing (100base - tx) ...................................................................................................................................................... 53 mii receive timing (100base - tx) ....................................................................................................................................................... 54 rmii timing ......................................................................................................................................................................................... 55 auto- negotiation timing ...................................................................................................................................................................... 56 mdc/mdio timing .............................................................................................................................................................................. 57 power - up/reset timing ...................................................................................................................................................................... 58 reset circuit .......................................................................................................................................................................... 59 reference circuits C led strap - in pins ................................................................................................................................ 60 reference clock C connection and s election ...................................................................................................................... 61 magnetics C connection and selection ................................................................................................................................ . 62 recommended land pattern ................................................................................................................................................ 64 package information (1) .......................................................................................................................................................... 65 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 6 revision 1.0 list of figures figure 1. auto - negotiation flow chart ................................................................................................................................ . 20 figure 2. ksz8051mnlu mii interface ................................................................................................................................ 22 figure 3. ksz8051rnlu rmii interface (25mhz clock mode) .......................................................................................... 25 figure 4. ksz8051rnlu rm ii interface (50mhz clock mode) .......................................................................................... 25 figure 5. ksz8051mnlu/rnlu to ksz8051mnlu/rnlu back - to - back copper repeater ............................................. 26 figure 6. ty pical straight cable connection ....................................................................................................................... 29 figure 7. typical crossover cable connection ................................................................................................................... 29 figure 8. local (digital) loopback ....................................................................................................................................... 30 figure 9. remote (analog) loopback .................................................................................................................................. 31 figure 10. ksz8051mnlu/rnlu power and ground connections ................................................................................... 35 figure 11. mii sqe timing (10base - t) ............................................................................................................................... 50 figure 12. mii transmit timing (10base - t) ......................................................................................................................... 51 figure 13. mii receive timing (10base - t) .......................................................................................................................... 52 figure 14. mii transmit timing (100base - tx) ..................................................................................................................... 53 figure 15. mii receive timing (100base - tx) ...................................................................................................................... 54 figure 16. rmii timing C data received from rmii ............................................................................................................ 55 figure 17. rmii timing C data input to rmii ....................................................................................................................... 55 figure 18. auto - negotiation fast link pulse (flp) timing ................................................................................................ . 56 figure 19. mdc/mdio timing .............................................................................................................................................. 57 figure 20. power - up/reset timing ...................................................................................................................................... 58 figure 21. recommended reset circuit .............................................................................................................................. 59 figure 22. recommended reset circuit for interfacing with cpu/fpga reset output ..................................................... 59 figure 23. reference circuits for led strapping pins ......................................................................................................... 60 figure 24. 25mhz crystal/oscillator reference clock connection ..................................................................................... 61 figure 25. 50mhz oscillator reference clock connection ................................................................................................ . 61 figure 26. typical magnetic interfa ce circuit ....................................................................................................................... 62 figure 27. recommended land pattern, 32 - pin (5mm x 5mm) qfn ................................................................................. 64 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 7 revision 1.0 list of tables ta ble 1. mii signal definition ............................................................................................................................................... 21 table 2. rmii signal definition ............................................................................................................................................. 23 table 3. mii signal connection for mii back - to - back mode ( 100base - tx copper repeater) ............................................ 26 table 4. rmii signal connection for rmii back - to - back mode (100base - tx copper repeater) ...................................... 27 table 5. mii management frame format for the ksz8051mnlu/rnlu ............................................................................ 28 table 6. mdi/mdi - x pin definition ....................................................................................................................................... 28 table 7. nand tree test pin order for ksz8051mnlu .................................................................................................... 32 table 8. nand tree test pin order for ksz8051rnlu ..................................................................................................... 33 table 9. ksz8051mnlu/rnlu power pin description ...................................................................................................... 35 table 10. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) .......................................................... 36 table 11. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) .......................................................... 36 table 12. typical current/power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) .......................................................... 37 table 13. mii sqe timing (10base - t) parameters ............................................................................................................. 50 table 14. mii transmit timing (10base - t) parameters ...................................................................................................... 51 table 15. mii receive timing (10b ase - t) parameters ........................................................................................................ 52 table 16. mii transmit timing (100base - tx) parameters .................................................................................................. 53 table 17. mii receive timing (100base - tx) parame ters ................................................................................................... 54 table 18. rmii timing parameters C ksz8051rnlu (25mhz input to xi pin, 50mhz output from ref_clk pin) ........... 55 table 19. rmii timing parameters C ksz8051rnlu (50mhz input to xi pin) ................................................................... 55 table 20. auto - negotiation fast link pulse (flp) timing parameters ............................................................................... 56 table 21. mdc/mdio timing parameters ........................................................................................................................... 57 table 22. power - up/reset timing parameters ................................................................................................................... 58 table 23. 25mhz crystal / reference clock selection criteria ........................................................................................... 61 table 24. 50mhz oscillator / reference clock selection criteria ....................................................................................... 61 table 25. magnetics selection criteria ................................................................................................................................ 63 table 26. compatible single - port 10/100 magnetics ........................................................................................................... 63 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 8 revision 1.0 pin configurationC ksz 8051mnlu 32 - pin (5mm x 5mm) qfn downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 9 revision 1.0 pin descriptionC ksz 8051mnlu pi n number pin name type (1) pin function 1 gnd gnd ground 2 vdd_1.2 p 1.2v core v dd (power supplied by ksz 8051mnlu ) decouple with 2.2 f and 0.1 f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd 4 rxm i/o physical receive or transmit signal ( ? differen tial) 5 rxp i/o physical receive or transmit signal (+ differential) 6 txm i/o physical transmit or receive signal ( ? differential) 7 txp i/o physical transmit or receive signal (+ differential) 8 xo o crystal feedback for 25mhz crystal this pin is a no connect if an oscillator or external clock source is used. 9 xi i crystal / oscillator / external clock input 25mhz 50ppm 10 rext i set phy transmit output current connect a 6.49k resistor to ground on this pin. 11 mdio ipu/opu management interface (mii) d ata i/o this pin has a weak pull - up, is open - drain , and requires an external 1.0k pull - up resistor. 12 mdc ipu management interface (mii) c lock input this clock pin is synchronous to the mdio data pin. 13 rxd3/ phyad0 ipu/o mii mode: mii receive data output[3] (2) config mode: the pull - up/pull - down value is latched as phyaddr[0] at the de - assertion of reset. see the strapping options section for details. 14 rxd2/ phyad1 ipd/o mii mode: mii receive data output[2] (2) config mode: the pull - up/pull - down value is latched as phyaddr[1] at the de - assertion of reset . see the strapping options section for details. 15 rxd1/ phyad2 ipd/o mii mode: mii receive data output[1] (2) config mode: the pull - up/pull - down value is latched as phyaddr[2] at the de - assertion of reset. see the strapping options section for details. 16 rxd0/ duplex ipu/o mii mode: mii receive data output[0] (2) config mode: the pull - up/pull - down value is latched as duplex at the de - assertion of reset . see the strapping options section for details. 17 v ddio p 3.3v, 2.5v, or 1.8v digital v dd 18 rxdv/ config2 ipd/o mii mode: mii receive data valid output config mode: the pull - up/pull - down value is latched as config2 at the de - assertion of reset . see the strapping option s section for details. 19 rxc/ b-cast_off ipd/o mii mode: mii receive clock output config mode: the pull - up/pull - down value is latched as b - cast_off at the de - assertion of reset. see the strapping options section fo r details. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 10 revision 1.0 pi n number pin name type (1) pin function 20 rxer/ iso ipd/o mii mode: mii receive error output config mode: the pull - up/pull - down value is latched as isolate at the de - assertion of reset . see the strapping options section for details. 21 intrp/ nand_tree# ipu/opu interrupt output: programmable interrupt output this pin has a weak pull - up, is open - drain, and requires an external 1.0k? pull - up resistor. config mode: the pull - up/pull - down value is latched as nand tree# at the de - assertion of reset . see the strapping options section for details 22 txc i /o mii mode: mii transmit clock output mii back - to - back mode: mii transmit clock input 23 txen i mii mode: mii transmit enable input 24 txd0 i mii mode: mii transmit data input[0] (3) 25 txd1 i mii mode: mii transmit data input[1] (3) 26 txd2 i mii mode: mii transmit data input[2] (3) 27 txd3 i mii mode: mii transmit data input[3] (3) 28 col/ config0 ipd/o mii mode: mii collision detect output config mode: the pull - up/pull - down value is latched as config0 at the de - assertion of reset. see the strappi ng options section for details. 29 crs/ config1 ipd/o mii mode: mii carrier sense output config mode: the pull - up/pull - down value is latched as config1 at the de - assertion of reset. see the strapping options section for details. 30 led0/ nwayen ipu/o led output: programmable led0 output config mode: latched as auto - negotiation enable (register 0h, bit [ 12 ] ) at the de - assertion of reset. see the strapping options section for deta ils . the led0 pin is programmable using register 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definiti on no link high off link low on led mode = [10], [11] reserved downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 11 revision 1.0 pi n number pin name type (1) pin function 31 led1/ speed ipu/o led output: programmable led1 output config mode: latched as speed (register 0h, bit [ 13 ] ) at the de - assertion of reset. see the strapping options section for details . the led1 pin is programmable using register 1fh bits [5:4], and is defined as follows. led mode = [00] speed pin state led definition 10base -t high off 100base - tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11] reserved 32 rst# ipu chip reset (active low) paddle gnd gnd ground note s: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see electrical characteristics for value). ipu/o = input with internal pull - up (see electrical characteristics for value ) during power - up/reset; output pin otherwise . ip d /o = input with internal pull - down (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see electrical characteristics for value) and output with internal pull - up (see electrical characteristics for value). 2. mii rx mode: the rxd[3:0] bits are synchronous with rxc. when rxdv is asserted, rxd[3:0] presents valid data to the mac. rxd[3:0] is invalid data from the phy when rxdv is de - asserted. 3. mii tx mode: the txd[3:0] bits are synchronous with txc. when txen is asserted, txd[3:0] pres ents valid data from the mac. txd[3:0] has no effect on the phy whe n txen is de - asserted. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 12 revision 1.0 strapping options C ksz 8051mnlu pin number pin name type (1) pin function 15 14 13 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o phyad[2:0] is latched at de - assertion of reset and is configurable to any value from 0 to 7 with phy address 1 as the default value. phy address 0 is assigned by default as the broadcast phy address, but it can be assigned as a unique phy address after pulling the b - cast_off strapping pin high or writing a 1 to register 16h, bit [9]. phy address bits [4:3] are set to 00 by default. 18 29 28 config2 config1 config0 ipd/o ipd/o ipd/o the config[2:0] strap - in pins are latched at the de - assertion of reset. config[2:0] mode 000 mii (default) 110 mii back - to -b ack 001 C 101, 111 reserved C not used 20 iso ipd/o i solate mode pull- up = enable pull- down (default) = disable at the de - assertion of reset, this pin value is latched into register 0h, bit [10]. 31 speed ipu/o s peed mode pull- up (default) = 100mbps pull- down = 10mbps at the de - assertion of reset, thi s pin value is latched into register 0h, bit [13] as the s peed s elect, and als o is latched into register 4h (auto - negotiation a d vertisement) as the speed capability support. 16 duplex ipu/o d uplex mode pull- up (default) = half -d uplex pull- down = full -du plex at the de - assertion of reset, this pin value is latched into register 0h, bit [8]. 30 nwayen ipu/o nway auto -n egotiation e nable pull- up (default) = enable a uto -n egotiation pull- down = disable auto - negotiation at the de - assertion of reset, this pin value is latched into register 0h, bit [12]. 19 b-cast_off ipd/o broadcast o ff C for phy address 0 pull- up = phy address 0 is set as an unique phy address pull- down (default) = phy address 0 is set as a broadcast phy address at the de - assertion of reset, this pin value is latched by the chip. 21 nand_tree# ipu/opu nand tree m ode pull- up (default) = disable pull- down = enable at the de - assertion of reset, this pin value is latched by the chip. note: 1. ipu/o = input with internal pull - up (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipd/o = input with internal pull - down (see electrical characteristics for value) during power - up/reset ; output pin otherwise. ipu/opu = input with internal pull - up (see electrical characteristics for value) and output with internal pull - up (see electrical characteristics for value) . the strap - in pins are latched at the de - assertion of reset. in some systems, the mac mii receive input pins may drive high/low during power - up or reset, and consequently cause the phy strap - in pins on the mii signals to be latched to unintended high/low states. in this case, external pull - ups (4.7 k ? ) or pull - downs (1.0k ? ) should be added on these phy strap - in pins to ensure that the intended values are strapped - in correctly. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 13 revision 1.0 pin configuration C ksz 8051rnlu 32 - pin (5mm x 5mm) qfn downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 14 revision 1.0 pin descriptionC ksz 8051rnlu pin number pin name type (1) pin fun ction 1 gnd gnd ground 2 vdd_1.2 p 1.2v core v dd (power supplied by ksz 8051rnlu ) decouple with 2.2 f and 0.1 f capacitors to ground. 3 vdda_3.3 p 3.3v analog v dd 4 rxm i/o physical receive or transmit signal ( ? differential) 5 rxp i/o physical receive or transmit signal (+ differential) 6 txm i/o physical transmit or receive signal ( ? differential) 7 txp i/o physical transmit or receive signal (+ differential) 8 xo o crystal feedback for 25mhz crystal this pin is a no connect if an oscillator or external clock source is used. 9 xi i 25mhz mode: 25mhz 50ppm crystal / oscillator / external clock input 50mhz mode: 50mhz 50ppm oscillator / external clock input 10 rext i set phy transmit output current connect a 6.49k resistor to ground on this pin . 11 mdio ipu/opu management interface (mii) d ata i/o this pin has a weak pull - up, is open - drain , and requires an external 1.0k pull - up resistor. 12 mdc ipu management interface (mii) c lock input this clock pin is synchronous to the mdio data pin. 13 phyad0 ipu/o the pull - up/pull - down value is latched as phyaddr[0] at the de - assertion of reset. see the strapping options section for details. 14 phyad1 ipd/o the pull - up/pull - down value is latched as phyaddr[1] at the de - assertion of reset. see the strapping options section for details. 15 rxd1/ phyad2 ipd/o r mii mode: r mii receive data output[1] (2) config mode: the pull - up/pull - down value is latched as phyaddr[2] at the de - asser tion of reset. see the strapping options section for details. 16 rxd0/ duplex ipu/o r mii mode: r mii receive data output[0] (2) config mode: the pull - up/pull - down value is latched as duplex at the de - assertion of res et. see the strapping options section for details. 17 vddio p 3.3v, 2.5v, or 1.8v digital v dd 18 crs_dv/ config2 ipd/o rmii mode: rmii carrier sense/receive data valid output / config mode: the pull - up/pull - down value is latched as config2 at the de - assertion of reset. see the strapping options section for details. 19 ref_clk / b-cast_off ipd/o rmii mode: 25mhz mode: this pin provides the 50mhz rmii reference clock output to the mac. see also xi (pin 9). 50mhz mode: this pin is a no connect. see also xi (pin 9). config mode: the pull - up/pull - down value is latched as b - cast_off at the de - assertion of reset. see the strapping options sectio n for details. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 15 revision 1.0 pin number pin name type (1) pin fun ction 20 rxer/ iso ipd/o r mii mode: r mii receive error output config mode: the pull - up/pull - down value is latched as isolate at the de - assertion of reset . see the strapping options section for details. 21 in trp/ nand_tree# ipu/opu interrupt output: programmable interrupt output this pin has a weak pull - up, is open - drain, and requires an external 1.0k ? pull - up resistor. config mode: the pull - up/pull - down value is latched as nand tree# at the de - assertion of reset. see the strapping options section for details. 22 nc - no connect C this pin is not bonded and can be left floating. 23 txen i rmii transmit enable input 24 txd0 i r mii transmit data input[0] (3) 25 txd1 i rmii transmit data input[1] (3) 26 nc - no connect C this pin is not bonded and can be left floating. 27 nc - no connect C this pin is not bonded and can be left floating. 28 config0 ipd/o the pull - up/pull - down value is latched as config0 at the de - assertion of reset. see the strapping options section for details. 29 config1 ipd/o the pull - up/pull - down value is latched as config1 at the de - assertion of reset. see the strapping options section for details. 30 led0/ nwayen ipu/o led output: programmable led0 output config mode: latched as auto - negotiation enable (register 0h, bit [ 12 ] ) at the de - assertion of reset. see the strapping options section for details. the led0 pin is programmable using register 1fh bits [5:4], and is defined as follows. led mode = [00] link/activity pin state led definition no link high off link low on activity toggle blinking led mode = [01] link pin state led definition no link high off link low on led mode = [10], [11] reserved downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 16 revision 1.0 pin number pin name type (1) pin fun ction 31 led1/ speed ipu/o led output: programmable led1 output config mode: latched as speed (register 0h, bit [ 13 ] ) at the de - assertion of reset. see the strapping options section for details. the led1 pin is programmable using register 1fh bits [5:4], and is defined as follows. led m ode = [00] speed pin state led definition 10base -t high off 100base - tx low on led mode = [01] activity pin state led definition no activity high off activity toggle blinking led mode = [10], [11] reserved 32 rst# ipu chip reset (active low ) paddle gnd gnd ground notes: 1. p = power supply. gnd = ground. i = input. o = output. i/o = bi - directional. ipu = input with internal pull - up (see electrical characteristics for value). ipu/o = input with internal pull - up (see electrical characteristics for value) during power - up/reset; output pin otherwise. ip d /o = input with internal pull - down (see electrical characteristics for val ue) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see electrical characteristics for value) and output with internal pull - up (see electric al characteristics for value). nc = pin is not bonded to the die. 2. rmii r x mode: the rxd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each clock per iod in which crs_dv is asserte d, two bits of recovered data are sent by the phy to th e mac . 3. rmii t x mode: the txd[1:0] bits are synchronous with the 50mhz rmii reference clock. for each cloc k period in which txen is asserted, two bits of data are received by the phy from the mac . downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 17 revision 1.0 strapping options C ksz 8051rnlu pin number pin name type (1) pin function 15 14 13 phyad2 phyad1 phyad0 ipd/o ipd/o ipu/o phyad[2:0] is latched at de - assertion of reset and is configurable to any value from 0 to 7 with phy address 1 as the default value. phy address 0 is assigned by default as the broadcast phy a ddress, but it can be assigned as a unique phy address after pulling the b - cast_off strapping pin high or writing a 1 to register 16h, bit [9]. phy address bits [4:3] are set to 00 by default. 18 29 28 config2 config1 config0 ipd/o ipd/o ipd/o the confi g[2:0] strap - in pins are latched at the de - assertion of reset. config[2:0] mode 00 1 rmii 101 r mii back - to - back 000, 010 C 100, 110, 111 reserved C not used 20 iso ipd/o isolate mode pull- up = enable pull- down (default) = disable at the de - assertion of reset, this pin value is latched into register 0h, bit [10]. 31 speed ipu/o speed mode pull- up (default) = 100mbps pull- down = 10mbps at the de - assertion of reset, this pin value is latched into register 0h, bit [13] as the speed select, and also is latched into register 4h (auto - negotiation advertisement) as the speed capability support. 16 duplex ipu/o duplex mode pull- up (default) = half - duplex pull- down = full - duplex at the de - assertion of reset, this pin value is latched into register 0h, bit [8]. 30 nwayen ipu/o nway auto - negotiation enable pull- up (default) = enable auto - negotiation pull- down = disable auto - negotiation at the de - assertion of reset, this pin value is latched into register 0h, bit [12]. 19 b-cast_off ipd/o broadcast off C for phy address 0 pull- up = phy address 0 is set as an unique phy address pull- down (default) = phy address 0 is set as a broadcast phy address at the de - assertion of reset, this pin value is latched by the chip. 21 nand_tree# ipu/opu nand tree mode pu ll - up (default) = disable pull- down = enable at the de - assertion of reset, this pin value is latched by the chip. note: 1. ipu/o = input with internal pull - up (see electrical characteristics for value) during power -u p/reset; output pin otherwise. ipd/o = input with internal pull - down (see electrical characteristics for value) during power - up/reset; output pin otherwise. ipu/opu = input with internal pull - up (see electrical characteristics for value) and output with internal pull - up (see electrical characteristics for value). the strap - in pins are latched at the de - assertion of reset. in some systems, the mac mii receive input pins may drive high/low during power - up or reset, and consequently cause the phy strap - in pins on the r mii signals to be latched to unintended high/low states. in this case, external pull - ups (4.7k ? ) or pull - downs (1.0k ? ) shoul d be added on these phy strap - in pins to ensure that the intended values are strapped - in correctly. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 18 revision 1.0 functional description: 10base - t/100base - tx transceiver the ksz 8051 is an integrated single 3.3v supply fast ethernet transceiver. it is fully compliant w ith the ieee 802.3 specification, and reduces board cost and simplifies board layout by using on - chip termination resistors for the two differential pairs and by integrating the regulator to supply the 1.2v core. on the copper media side, the ksz 8051 support s 10base - t and 100base - tx for transmission and reception of data over a standard cat - 5 unshielded twisted pair (utp) cable, and h p a uto mdi/mdi - x for reliable detection of and correction for straight - through and crossover cables. on the mac processor side, the ksz 8051mnlu offers the media independent interface (mii) and the ksz 8051rnlu offers the reduced media independent interface (rmii) for direct connection with mii and rmii compliant ethernet mac processors and switches, respectively . the mii management bus option gives the mac processor complete access to the ksz 8051 control and status registers. additionally, an interrupt pin eliminates the need for the processor to poll for phy status c hange. the ksz 8051mnlu / rnlu is used to refer to both ksz 8051mnlu a nd ksz 8051rnlu versions in this data sheet. 100base - tx transmit the 100base - tx transmit function performs parallel - to - serial conversion, 4b/5b encoding, scrambling, nrz - to - nrzi conversion, and mlt3 encoding and transmission. the circuitry starts with a pa rallel - to - serial conversion, which converts the mii data from the mac into a 125mhz serial bit stream. the data and control stream is then converted into 4b/5b coding and followed by a scrambler. the serialized data is further converted from nrz - to - nrzi fo rmat, and then transmitted in mlt3 current output. the output current is set by an external 6.49k 1% resistor for the 1:1 transformer ratio. the output signal has a typical rise/fall time of 4ns and complies with the ans i tp - pmd standard regarding amplitude balance, overshoot, and timing jitter. the wave - shaped 10base - t output is also incorporated into the 100base - tx transmitter. 100base - tx receive the 100base - tx receiver function performs adaptive equalization, dc restoration, mlt3 - to - nrzi conversion, data and clock recovery, nrzi - to - nrz conversion, de - scrambling, 4b/5b decoding, and serial - to - paral lel conversion. the receiving side starts with the equalization filter to compensate for inter - symbol interference (isi) over the twisted pair cable. because the amplitude loss and phase distortion is a function of the cable length, the equalizer must adj ust its characteristics to optimize performance. in this design, the variable equalizer makes an ini tial estimation based on comparisons of incoming signal strength against some known cable characteristics, then tunes itself for optimization. this is an ongoing process and self - adjusts against environmental changes such as temperature variations. next, the equalized signal goes through a dc - restoration and data - conversion block. the dc - restoration circuit compensate s for the effect of baseline wander and im prove s the dynamic range. the differential data - conversion circuit converts mlt3 format back to nrzi. the slicing threshold is also adaptive. the clock - recovery circuit extracts the 125mhz clock from the edges of the nrzi signal. this rec overed clock is then us ed to convert the nrzi signal to nrz format. this signal is sent through the de - scrambler , then the 4b/5b decoder. finally, the nrz serial data is converted to mii format and provided as the input data to the mac. scrambler/de - scrambler (100base - tx o nly) the scrambler spreads the power spectrum of the transmitted signal to reduce electromagnetic int erference (emi) and baseline wander. the de - scrambler recovers the scrambled signal. 10base - t transmit the 10base - t drivers are incorporated with the 100ba se - tx drivers to allow for transmission using the same magnetic. the drivers perform internal wave - shaping and pre - emphasis, and output 10base - t signals with a typical amplitude of 2.5v peak. the 10base - t signals have harmonic contents that are at least 27db below the fundamental frequency when driven by an all - ones manchester - encoded signal. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 19 revision 1.0 10base - t receive on the receive side, input buffer and level detecting squelch circuits are used . a differential input receiver circuit and a phase - locked loop ( pll ) p erforms the decoding function. the manchester - encoded data stream is separated into clock signal and nrz data. a squelch circuit rejects signals with levels less than 400 mv , or with short pulse widths , to prevent noise at the rxp and rxm inputs from falsely trigger ing the decoder. when the input exceeds the squelch limit, the pll locks onto the incoming signal and the ksz 8051mnlu / rnlu decodes a data frame. the receive clock is kept active during idle periods between data reception s. sqe and jabber function (10base - t only) in 10base - t operation, a short pulse is put out on the col pin after each frame is transmitted. this sqe t est is needed to test the 10base - t transmit/receive path. if transmit enable (txen) is high for more than 20ms (jabbering), the 10base - t transmitter is disabled and col is asserted high. if txen is then driven low for m ore than 250ms, the 10base - t transmitter is re - enabled and col is de - asserted (returns to low). pll clock synthesizer the ksz 8051mnlu / rnlu generates all internal clocks and all external clocks for system timing from an external 25mhz crystal, oscillator, or reference clock. for the ksz 8051rnlu in rmii 50mhz clock mode, these clocks are generated from an external 50mhz oscillator or system clock. auto - negotiation the ksz 8051mnlu / rnlu conforms to the auto - negotiation protocol, defined in clause 28 of the ieee 802.3 specification. auto - negotiation allows unshielded twisted pair ( utp ) link partners to select the highest common mode of operation. during auto - negotiation, link partners advertise capabilities across the utp link to each other and then compare their own capabilities with those they received from their link partners. the highest speed and duplex setting that is common to the two link partners is selected as the mode of operation. the following list shows the speed and duplex operation mode from highest to lowest priorit y. ? priority 1: 100base - tx, full - duplex ? priority 2: 100base - tx, half - duplex ? priority 3: 10base - t, full - duplex ? priority 4: 10base - t, half - duplex i f auto - negotiation is not supported or the ksz 8051mnlu / rnlu link partner is forced to bypass auto - negotiation, then the ksz 8051mnlu / rnlu sets its operating mode by observing the signal at its receiver. this is known as parallel detec tion, which allows the ksz 8051mnlu / rnlu to establish a link by listening for a fixed signal protocol in the absence of the auto - negotiation advertisement protocol. auto - negotiation is enabled by either hardware pin strapping (nwayen, pin 30 ) or software (register 0h, bit [12]). by default, auto - negotiation is enabled after power - up or hardware reset. after that , auto - negotiation can be enabled or disabled by register 0h, bit [12]. if auto - negotiation is disabled, the speed is set by register 0h, bit [13], and the duplex is set by register 0h, bit [8]. the auto - negotiation link - up process is shown in figure 1 . downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 20 revision 1.0 figure 1 . auto - negotiation flow chart mii interface (ksz 8051mnlu only) the media independent interface (mii) is compliant with the ieee 802.3 specification. it provides a common interface between mii phys and macs, and has the following key characteristics: ? pin count is 15 pins (6 pins for data transmission, 7 pins for data reception, and 2 pins for carrier and collision indication). ? 10mbps and 100mbps data rates are supported at both half - and full - duplex. ? data transmission and reception are independent and belong to separate signal groups. ? transmit data and receive data are each 4 bit s wide, a nibble. by default, the ksz 8051mnlu is configured to mii mode after it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 9, 8), or an external 25mhz clock source (oscil lator) connected to xi. ? the config[2:0] strapping pins (pins 18 , 29 , 28 ) set to 000 (default setting) . mii signal definition table 1 describes the mii signals. refer to clause 22 of the ieee 802.3 specification for detail ed information. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 21 revision 1.0 mii signal name direction ( with respect to phy, ksz 8051mnlu signal) direction (with respect to mac) description txc output input transmit clock (2.5mhz for 10mbps; 25mhz for 100mbps) txen input output transmit enable txd[3:0] input output transmit data[3:0] rxc output input re ceive clock (2.5mhz for 10mbps; 25mhz for 100mbps) rxdv output input receive data valid rxd[3:0] output input receive data[3:0] rxer output input, or (not required) receive error crs output input carrier sense col output input collision detection t able 1 . mii signal definition transmit clock (txc) txc is sourced by the phy. it is a continuous clock that provides the timing reference for t xen and txd[3:0]. txc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. t ransmit enable (txen) txen indicates that the mac is presenting nibbles on txd[3:0] for transmission. it is asserted synchronously with the first nibble of the preamble and remains asserted while all nibbles to be transmitted are presented on the mii . it i s negated before the first txc following the final nibble of a frame. txen transitions synchronously with respect to txc. transmit data[3:0] (txd[3:0]) txd[3:0] transitions synchronously with respect to txc. when txen is as serted, txd[3:0] are accepted by the phy for transmission. txd[3:0] is 00 to indicate idle when txen is de - asserted. values other than 00 on txd[3:0] while txen is de - asserted are ignored by the phy. receive clock (rxc) rxc provides the timing reference for rxdv, rxd[3:0], and rxer. ? in 10mbps mode, rxc is recovered from the line while the carrier is active. rxc is derived from the phys refere nce clock when the line is idle or the l ink is down. ? in 100mbps mode, rxc is continuously recovered from the line. if the link is down, rxc is derive d from the phys reference clock. rxc is 2.5mhz for 10mbps operation and 25mhz for 100mbps operation. receive data valid (rxdv) rxdv is driven by the phy to indicate that the phy is presenting recovered and decoded nibb les on rxd[3:0]. ? in 10mbps mode, rxdv is asserted with the first nibble of the start - of - frame delimiter ( sfd ) , 5d, and remains asserted until the end of the frame. ? in 100mbps mode, rxdv is asserted from the first nibble of the preamble to the last nibble of the fra me. rxdv transitions synchronously with respect to rxc. receive data[3:0] (rxd[3:0]) rxd[3:0] transitions synchronously with respect to rxc. for each clock period in which rxdv is asserted, rxd[3:0] transfers a nibble of recovered data from the phy. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 22 revision 1.0 receive error (rxer) rxer is asse rted for one or more rxc periods to indicate that a symbol error (for example, a coding error that a phy can detect that may otherwise be undetectable by the mac sub - layer) was detected somewhere in the frame being transferred from the phy. rxer transitions synchronously with respect to rxc. while rxdv is de - asserted, rxer has no effect on the mac. carrier sense (crs) crs is asserted and de - asserted as follows: ? in 10mbps mode, crs assertion is based on the reception of valid preambles. crs de - assertion is b ased on the reception of an end - of - frame (eof) marker. ? in 100mbps mode, crs is asserted when a start - of - stream delimiter or /j/k symbol pair is detected. crs is de - asserted when an end - of - stream delimiter or /t/r symbol pair is detected. additionally, the pma layer de - asserts crs if idle symbols are received without /t/r. collision (col) col is asserted in half - duplex mode whenever the transmitter and receiver are simultaneously active on the line. this inform s the mac that a collision has occurred during its transmission to the phy. col transitions asynchronously with respect to txc and rxc. mii signal diagram the ksz 8051mnlu mii pin connections to the mac are shown in figure 2 . figure 2 . ksz 8051mnlu mii interface downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 23 revision 1.0 rmii data interface (ksz 8051rnlu only) the reduced media independent interface (rmii) specifies a low pin count media independent interface (mii). i t provides a common interface between physical layer and mac layer devices, and has the following ke y characteristics: ? pin count is 8 pins (3 pins for data transmission, 4 pins for data reception, and 1 pin for the 50mhz reference clock ). ? 10mbps and 100mbps data rates are supported at both half - and full - duplex. ? data transmission a nd reception are independent and belong to separate signal groups. ? transmit data and receive data are each 2 bits wide, a dibit . rmii C 25mhz clock mode the ksz 8051rnlu is configured to rmii C 25mhz clock mode after it is powered up or hardware reset with the following: ? a 25mhz crystal connected to xi, xo (pins 9, 8), or an external 25mhz clock source (oscil lator) connected to xi. ? the config[2:0] strapping pins (pins 18, 29, 28) set to 001. ? register 1fh, bit [7] is set to 0 (default value) to select 25mhz c lock mode. rmii C 50mhz clock mode the ksz 8051rnlu is configured to rmii C 50mhz clock mode after it is powered up or hardware reset with the following: ? an external 50mhz clock source (oscillator) connected to xi (pin 9). ? the config[2:0] strapping pins (pins 18, 29, 28) set to 001. ? register 1fh, bit [7] is set to 1 to select 50mhz clock mode. r mii signal definition table 2 describes the r mii signals. refer to rmii specification v1.2 for detailed information. r mii s ignal name direction (with respect to phy, ksz 8051rnlu signal) direction (with respect to mac) description ref_clk output (25mhz clock mode) / (50mhz clock mode) input/ input or synchronous 50mhz reference clock for receive, transmit, and control interface txen input output transmit enable txd[1:0] input output transmit data[1:0] crs_dv output input carrier sense/receive data valid rxd[1:0] output input receive data[1:0] rxer output input, or (not required) receive error table 2 . r mii signal definition reference clock (ref_clk) ref_clk is a continuous 50mhz clock that provides the timing reference for tx en, txd[1:0], crs_dv, rxd[1:0], and rx_er. for 25mhz clock mode, the ksz 8051rnlu generates and outputs the 50mhz rmii ref_clk to the mac at ref_clk (pin 19). for 50mhz clock mode, the ksz 8051rnlu takes in the 50mhz rmii ref_clk from the mac or system board at xi (pin 9) and leaves the ref_clk (pin 19) as a no connect. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 24 revision 1.0 transmit enable (txen) txen i ndicates that the mac is presenting dibits on txd[ 1 :0] for transmission. it is asserted synchronously with the first dibit of the preamble and remains asserted while all dibits to be transmitted are presented on the r mii. it is negated before the first ref _clk following the final dibit of a frame. txen transitions synchronously with respect to ref_clk . transmit data[1:0] (txd[1:0]) txd[1:0] transitions synchronously with respect to ref_clk. when txen is ass erted, the phy accepts txd[1:0] for transmission. t xd[1:0] is 00 to indicate idle when txen is de - asserted. the phy ignores values other than 00 on txd[1:0] while txen is de - asserted. carrier sense / receive data valid (crs_dv) the phy asserts crs_dv when the receive medium is non - idle. it is asserted asyn chronously when a carrier is detected . this happens when squelch is passed in 10mbps mode, and when two non - contiguous 0s in 10 bits are detected in 100mbps mode. loss of carrier results in the de - assertion of crs_dv. while carrier detection criteria are met, crs_dv remains asserted continuously from the first recovered dibit of the frame through the final recovered dibit. it is negated before the first ref_clk that follows the final dibit. the data on rxd[1:0] is considered valid after crs_dv is asserted. however, because the assertion of crs_dv is async hronous relative to ref_clk, the data on rxd[1:0] is 00 until receive signals are proper ly decod ed . receive data[1:0] (rxd[1:0]) rxd[1:0] transitions synchronously with respect to ref_clk. for each clock period in which crs_dv is asserted, rxd[1:0] transfers two bits of recovered data from the phy. rxd[1:0] is 00 to indicate idle when crs_dv is de - asserted. the mac ignores values other than 00 on rxd[1:0] while crs_dv is de - asserted. receive error (rxer) rxer is asserted for one or more ref_clk periods to indicate that a symbol error (for example, a coding error that a phy can detect that may otherwise be undetectable by the mac sub - layer) was detected somewhere in the frame being transferred from the phy. rxe r transitions synchronously with respect to ref_clk . . while crs_dv is de - asserted, rxer has no effect on the mac. collision detection (col) the mac regenerates the col signal of the mii from txen and crs_dv. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 25 revision 1.0 r mii signal diagram the ksz 8051rnlu rmii pin connections to the mac for 25mhz c lock m ode are shown in figure 3 . the connections for 50mhz clock mode are shown in figure 4 . figure 3 . ksz 8 051rnlu rmii interface (25mhz clock mode) figure 4 . ksz 8051rnlu rmii interface (50mhz clock mode) downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 26 revision 1.0 back -to- back mode C 100mbps copper repeater two ksz 8051mnlu / rnlu devices can be connected back - to - back to form a 100base - tx c opper repeater. figure 5 . ksz 8051mnlu / rnlu to ksz 8051mnlu / rnlu back -to- back copper repeater mii back - to - back mode (ksz 8051mnlu only) in mii b ack - to -b ack mode, a ksz 8051mnlu interfaces with another ksz 8051mnlu to provide a com plete 100mbps copper repeater solution. t he ksz 8051mnlu devices are configured to mii b ack - to -b ack mode after power - up or reset with the following: ? strapping pin config[2:0] (pins 18 , 29 , 28 ) set to 110 ? a common 25mhz reference clock connected to xi (pin 9) of both ksz 8051mnlu devices ? mii signals connected as shown in table 3 ksz 8051mnlu (100base - tx copper) [device 1] ksz 8051mnlu (100base - tx copper) [device 2] pin name pin number pin type pin name pin number pin t ype rxc 19 output txc 22 input rxdv 18 output txen 23 input rxd3 13 output txd3 27 input rxd2 14 output txd2 26 input rxd1 15 output txd1 25 input rxd0 16 output txd0 24 input txc 22 input rxc 19 output txen 23 input rxdv 18 output txd3 27 input r xd3 13 output txd2 26 input rxd2 14 output txd1 25 input rxd1 15 output txd0 24 input rxd0 16 output table 3 . mii signal connection for mii back - to - back mode (100base - tx copper repeater) downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 27 revision 1.0 rmii back - to - back mode (ksz 8051rnlu on ly) in rmii back - to - back mode, a ksz 8051rnlu interfaces with another ksz 8051rnlu to provide a complete 100mbps copper repeater solution. t he ksz 8051rnlu devices are configured to rmii back - to - back mode after power - up or reset with the following: ? strapping pin config[2:0] (pins 18, 29, 28) set to 101 ? a common 50mhz reference clock connected to xi (pin 9) of both ksz 8051rnlu devices ? rmii signals connected as shown in table 4 ksz 8051rnlu (100base - tx copper) [device 1] ksz 8051rnlu (100base - tx copper) [device 2] pin name pin number pin type pin name pin number pin type crsdv 18 output txen 23 input rxd1 15 output txd1 25 input rxd0 16 output txd0 24 input txen 23 input crsdv 18 output txd1 25 input rxd1 15 output txd0 24 input rxd0 16 output table 4 . rmii signal connection for rmii back - to - back mode (100base - tx copper repeater) mii management (miim) interface the ksz 8051mnlu / rnlu supports the ieee 802.3 mii m anagement i nterface, also known as the management data input/ output (mdio) i nterface. this interface allows an upper - layer device , such as a mac processor, to monitor and control the state of the ksz 8051mnlu / rnlu . an external device with miim capability is used to read the phy status and/or configure the phy settings. more detail s about the miim interface can be found in clause 22.2.4 of the ieee 802.3 specification. the miim interface consists of the following: ? a physical connection that incorporates the clock line (mdc) and the data line (mdio). ? a specific protocol that operates across the physical connection mentioned earlier, which allows the external controller to communicate with one or more phy devices. ? a set of 16 - bit mdio registers. r egisters [0:8] are standard registers, and their functions are defined in the ieee 802.3 specification. the additional registers are provided for expanded functionality. see the register map section for details. as the default, the ksz 8051mnlu / rnlu supports uni que phy addresses 1 to 7, and broadcast phy address 0. the latter is defined in the ieee 802.3 specification, and can be used to read/write to a single ksz 8051mnlu / rnlu device, or write to multiple ksz 8051mnlu / rnlu devices simultaneously. phy address 0 can optionally be disabled as the broadcast address by either hardware pin strapping (b - cast_off, pin 19 ) or software (register 16h, bit [9]), and assigned as a unique phy address. the phyad[2:0] strapping pins are used to assign a unique phy address between 0 and 7 t o each ksz 8051mnlu / rnlu device. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 28 revision 1.0 table 5 shows the mii management frame format for the ksz 8051mnlu / rnlu . preamble start of frame read/write op code phy address bits [4:0] reg address bits [4:0] ta dat a b its [15:0] idle read 32 1s 01 10 00aaa rrrrr z0 dddddddd_dddddddd z write 32 1s 01 01 00aaa rrrrr 10 dddddddd_dddddddd z table 5 . mii management frame format for the ksz 8051mnlu / rnlu interrupt (intrp) intrp (pin 21 ) is an optional interrupt signal that is used to inform the external controller that there has been a status update to the ksz 8051mnlu / rnlu phy register. bits [15:8] of register 1bh are the interrupt control bits to enable and disable the conditions for asserting t he intrp signal. bits [7:0] of register 1bh are the interrupt status bits to indicate which interrupt conditions have occurred. the interrupt status bits are cleared after reading r egister 1bh. bit [9] of r egister 1fh sets the interrupt level to active high or active low. the default is active lo w. the mii management bus option gives the mac processor complete access to the ksz 8051mnlu / rnlu control and status registers. additionally, an interrupt pin eliminates the need for the processor t o poll the phy for status change. hp auto mdi/mdi-x hp auto mdi/mdi - x configuration eliminates the need to decide whether to use a straight cable or a crossover cable between the ksz 8051mnlu / rnlu and its link partner. this feature allows the ksz 8051mnlu / rnlu to use either type of cable to connect with a link partner that is in either mdi or mdi - x mode. the auto - sense function detects transmit and rece ive pairs from the link partner and assigns transmit and receive pairs to the ksz 8051mnlu / rnlu accordingly. hp auto mdi/mdi -x is enabled by default. it is disabled by writing a 1 to register 1fh, bit [13]. mdi and mdi - x mode is selected by register 1fh, bit [14] if hp auto mdi/mdi - x is disabled. an isolation transformer with symmetrical transmit and receive data paths is recomm ended to support auto mdi/mdi - x. table 6 shows how the ieee 802.3 standard defines mdi and mdi - x. mdi mdi -x rj - 45 pin signal rj - 45 pin signal 1 tx+ 1 rx+ 2 tx ? 2 rx ? 3 rx+ 3 tx+ 6 rx ? 6 tx ? table 6 . mdi/mdi - x pin definition straight cable a straight cable connects a n mdi device to a n mdi - x device, or a n mdi - x device to a n mdi device. figure 6 shows a typical straight cable connection between a nic card (mdi device) and a switch or hub (mdi - x device). downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 29 revision 1.0 figure 6 . typical straight cable connection crossover cable a crossover cable connects a n mdi device to another mdi device, or a n mdi - x device to another mdi - x devi ce. figure 7 shows a typical crossover cable connection between two switches or hubs (two mdi - x devices). figure 7 . typical crossover cable connection downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 30 revision 1.0 loopback mode the ksz 8051mnlu /r nlu supports the following loopback operations to verify analog and/or digital data paths. ? local (d igital) l oopback ? remote (a nalog) l oopback local (digital) loopback this loopback mode checks the mii /rmii transmit and receive data paths between the ksz 8051mnlu / rnlu and the external mac, and is s u pported for both speeds (10/100mbps) at full - duplex. the loopback data path is shown in figure 8 . 1. the mii/rmii mac transmits frames to the ksz 8051mnlu / rnlu . 2. frames are wrapped around inside the ksz 8051mnlu / rnlu . 3. the ksz 8051mnlu / rnlu transmits frames back to the mii/rmii mac. figure 8 . local (digital) loopback the following programming action and register settings are used for local loopback mode . for 10 /1 00 mbps loopback, set r egister 0h, ? bit [14] = 1 // enable local l oopback mode ? bit [13] = 0/1 // select 10mbps /100mbps speed ? bit [12] = 0 // disable a uto -n egotiation ? bit [8] = 1 // select full - duplex mode remote (analog) loopback this lo opback mode checks the line (differential pairs, transformer, rj - 45 connector, ethernet cable) transmit and receive data paths between the ksz 8051mnlu / rnlu and its link partner, and is supported for 100 base -tx full - duplex mode only. the loopback data path is shown in figure 9 . 1. the fast ethernet (100base - tx) phy l ink p artner transmits frames to the ksz 8051mnlu / rnlu . 2. frames are wrapped around inside the ksz 8051mnlu / rnlu . 3. the ksz 8051mnlu / rnlu transmits frames back to t he fast ethernet (100base - tx) phy l ink p artner. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 31 revision 1.0 figure 9 . remote (analog) loopback the following programming steps and register settings are used for remote l oopback mode. 1. set register 0h, ? bits [13] = 1 // select 10 0mbps sp eed ? bit [12] = 0 // disable auto -n egotiation ? bit [8] = 1 // selec t full - duplex mode or just auto - negotiate and link up at 100base - tx full - duplex mode with the link partner. 2. set register 1 f h, ? bit [ 2 ] = 1 // enable remote l oopback mode linkmd ? cable diagnostic the linkmd function uses time - domain reflectometry (tdr) to analyze the cabling plant for common cabling problems . these include open circuits, short circuits , and impedance mismatches. linkmd works by sending a pulse of known amplitude and duration down the mdi or mdi - x pair , then analyzing the shape of the reflected signal to determine the type of fault . the time duration for the reflected signal to return provides the approximate distance to the cabling fault. the linkmd function processes this tdr information and presents it as a numerical value that can be translated to a cable distance. linkmd is initiated by accessing register 1dh, the linkmd control/statu s r egister, in conjunction with register 1fh, the phy control 2 r egister. the latter register is used to disable a uto mdi/mdi - x and to select either mdi or mdi - x as the cable differential pair for testing. nand tree support the ksz 8051mnlu / rnlu provides parametric nand tree support for fault detection between chip i/ os and board. the nan d tree is a chain of nested nand gates in which each ksz 8051mnlu / rnlu digital i/o (nand tree input) pin is an input to one nand gate along the chain. at the end of the chain, the crs/config1 pin provides the out put for the nested nand gates. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 32 revision 1.0 the nand tree test process includes: ? enabling nand tree mode ? pulling all nand tree input pins high ? driving each nand tree input pin low, sequentially , according to the nand tree pin order ? checking the nand tre e output to make sure there is a toggle high - to - low or low -to- high for each nand tree input driven low table 7 and table 8 list the nand tree pin orders for ksz 8051mnlu and ksz 8051rnlu , respectively. pin number pin name nand tree description 11 mdio input 12 mdc input 13 rxd3 input 14 rxd2 input 15 rxd1 input 16 rxd0 input 18 rxdv input 19 rxc input 20 rxer input 21 intrp input 22 txc input 23 txen input 24 txd0 input 25 txd1 input 26 txd2 input 27 txd3 input 30 le d0 input 31 led1 input 28 col input 29 crs output table 7 . nand tree test pin order for ksz 8051mnlu downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 33 revision 1.0 pin number pin name nand tree description 11 mdio input 12 mdc input 13 phyad0 input 14 phyad1 input 15 rxd1 input 16 rxd0 input 18 crs_dv input 19 ref_clk input 20 rxer input 21 intrp input 23 txen input 24 txd0 input 25 txd1 input 30 led0 input 31 led1 input 28 config0 input 29 config1 output table 8 . nand tree test pin order for k sz 8051rnlu nand tree i/o testing use the following procedure to check for faults on the ksz 8051mnlu / rnlu digital i/o pin connections to the board: 1. enable nand tree mode using either hardware (nand_tree#, pin 21 ) or software (register 16h, bit [5]). 2. use board logic to drive all ksz 8051mnlu / rnlu nand tree input pins high. 3. use board logic to drive each nand tree input pin, in ksz 8051mnlu / rnlu nand t ree pin order, as follow s: a. toggle the first pin (mdio) from high to low, and verify that the crs/config1 pin swi tch es from high to low to indicate that the first pin is connected properly. b. leave the first pin (mdio) low. c. toggle the second pin (mdc) from high to low, and verify that the crs/config1 pin switch es from low to high to indicate that the second pin is connected properly. d. leave the first pin (mdio) and the second pin (mdc) low. e. toggle the third pin (rxd3 /phyad0) ) from high to low, and verify that the crs/config1 pin switch es from high to low to indicate that the third pin is connected properly. f. continue with this sequence until all ksz 8051mnlu / rnlu nand tree input pins have been toggled. each ksz 8051mnlu / rnlu nand tree input pin must cause the crs/config1 output pin to toggle high - to - low or low - to - high to indicate a good connection. if the crs pin fails to toggle when the ksz 8051mnlu / rnlu input pin toggles from high to low, the input pin has a fault. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 34 revision 1.0 power management the ksz 8051mnlu / rnlu incorporates a number of power - management modes and features that provide methods to consume less energy. these are discussed in the following sections. power - saving mode power -s aving m ode is used to reduce the transceiver power consumption when the cable is unplugged. it is enabled by writing a 1 to register 1fh, bit [10], and is in effect when auto - negotiation mode is enabled and the cable is disconnected (no link). in this mode, the ksz 8051mnlu / rnlu shuts down all transceiver blocks, except for the transmitter, energy detect , and pll circuits. by default, power - saving mode is disabled after power - up. energy - detect power - down mode energy - detect power - down (edpd) m ode is used to further reduce transceiver power consumption when the cable is un plugged. it is enabled by writing a 0 to register 18h, bit [11], and is in effect when auto - negotiation mode is enabled and the ca ble is disconnected (no link). edpd m ode works with the pll off (set by writing a 1 to register 10h, bit [4] to automatically turn the pll off in edpd m ode) to turn off all ksz 8051mnlu / rnlu transceiver blocks except the transmitter and energy - detect cir cuits. power can be reduced further by extending the time interval between transmissions of link pulses to check for the presence of a link partner. the periodic transmission of link pulses is needed to ensure the ksz 8051mnlu / rnlu and its link partner, when operating in the same low - power state and with auto mdi/mdi - x disabled, can wake up when the cable is connected between them. by default, energy - detect power - down mode is disabled after power - up. power - down mode power - down m ode is used to power down the ksz 8051mnlu / rnlu device when it is not in use after power - up. it is enabled by writing a 1 to register 0h, bit [11]. in this mode, the ksz 8051mnlu / rnlu disables all internal functions except the mii management interface. t he ksz 8051mnlu / rnlu exits (disa bles) power - down m ode after register 0h, bit [11] is set back to 0. slow - oscillator mode slow - oscillator mode is used to disconnect the input reference crystal/clock on xi (pin 9 ) and select the on - chip slow oscillator when the ksz 8051mnlu / rnlu device is not in use after power - up. it is enabled by writing a 1 to register 11h, bit [5]. slow -o scillator mode works in conjunction with power - down mode to put the ksz 8051mnlu / rnlu device in the lowest power state , with all internal functions disabled except the mii management interface. to properly exit this mode and return to normal phy operation, use the following programming sequence: 1. disable slow -o scillator m ode by writing a 0 to register 11h, bit [5]. 2. disable power -d own m ode by writing a 0 to register 0h, bit [11]. 3. initiate software reset by writing a 1 to register 0h, bit [15]. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 35 revision 1.0 reference circuit for power and ground connections the ksz 8051mnlu / rnlu is a single 3.3v supply device with a built - in regulator to supply the 1.2v core. the power and groun d connections are shown in figure 10 and table 9 for 3.3v vddio. figure 10 . ksz 8051mnlu / rnlu power and ground connections power pin pin numb er description vdd_1.2 2 decouple with 2.2 f and 0.1 f capacitors to ground. vdda_3.3 3 connect to boards 3.3v supply through a ferrite bead. decouple with 22 f and 0.1 f capacitors to ground. vddio 17 connect to boards 3.3v supply for 3.3v vddio. dec ouple with 22 f and 0.1 f capacitors to ground. table 9. ksz 8051mnlu / rnlu power pin description downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 36 revision 1.0 typical current/power consumption table 10 through table 12 show typical values for current consumption by the transce iver (vdda_3.3) and digital i/o (vddio) power pins and typical values for power consumption by the ksz 8051mnlu / rnlu device for the indicated nominal operating voltages. these current and power consumption values include the trans mit driver current and on - chip regulator current for the 1.2v core. transceiver (3.3v), digital i/os (3.3v) condition 3.3v transceiver (vdda_3.3) 3.3v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 12 152 100base - tx full - duplex @ 100% utilization 34 13 155 10base - t link - up (no traffic) 14 11 82.5 10base - t full - duplex @ 100% utilization 30 11 135 power - saving mode (reg. 1fh, bit [10] = 1) 14 10 79.2 edpd mode (reg. 18h, b it [11] = 0) 10 10 66.0 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.77 1.54 17.5 software power - down mode (reg. 0h, bit [11] =1) 2.59 1.51 13.5 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 1 1h, bit [5] =1) 1.36 0.45 5.97 table 10 . typical current /power consumption (vdda_3.3 = 3.3v, vddio = 3.3v) transceiver (3.3v), digital i/os (2.5v) condition 3.3v transceiver (vdda_3.3) 2.5v digital i/os (vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 140 100base - tx full - duplex @ 100% utilization 34 12 142 10base - t link - up (no traffic) 15 10 74.5 10base - t full - duplex @ 100% utilization 27 10 114 power -s aving m ode (reg. 1fh, bit [10] = 1) 15 10 74.5 edpd m ode (reg. 18h, bit [11] = 0) 11 10 61.3 edpd m ode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 3.55 1.35 15.1 software p ower - down mode (reg. 0h, bit [11] =1) 2.29 1.34 10.9 software power -d own mode (reg. 0h, bit [11] =1) and slow - oscillator m ode (reg. 11h, bit [5] =1) 1.15 0.29 4.52 table 11 . typical current/ power consumption (vdda_3.3 = 3.3v, vddio = 2.5v) downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 37 revision 1.0 transceiver (3.3v), digital i/os (1.8v) condition 3.3v transceiver (vdda_3.3) 1.8v digital i/os ( vddio) total chip power ma ma mw 100base - tx link - up (no traffic) 34 11 132 100base - tx full - duplex @ 100% utilization 34 12 134 10base - t link - up (no traffic) 15 9.0 65.7 10base - t full - duplex @ 100% utilization 27 9.0 105 power - saving mode (reg. 1fh, bit [10] = 1) 15 9.0 65.7 edpd mode (reg. 18h, bit [11] = 0) 11 9.0 52.5 edpd mode (reg. 18h, bit [11] = 0) and pll off (reg. 10h, bit [4] = 1) 4.05 1.21 15.5 software power - down mode (reg. 0h, bit [11] =1) 2.79 1.21 11.4 software power - down mode (reg. 0h, bit [11] =1) and slow - oscillator mode (reg. 11h, bit [5] =1) 1.65 0.19 5.79 table 12 . typical current / power consumption (vdda_3.3 = 3.3v, vddio = 1.8v) downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 38 revision 1.0 register map register number (hex) description 0h basic control 1h b asic status 2h phy identifier 1 3h phy identifier 2 4h auto- negotiation advertisement 5h auto- negotiation link partner ability 6h auto- negotiation expansion 7h auto- negotiation next page 8h link partner next page ability 9h reserved 10h digital re served control 11h afe control 1 12h C 14h reserved 15h rxer counter 16h operation mode strap override 17h operation mode strap status 18h expanded control 19h C 1ah reserved 1bh interrupt control/status 1ch reserved 1dh linkmd control/status 1e h phy control 1 1fh phy control 2 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 39 revision 1.0 register description address name description mode (1) default register 0h C basic control 0.15 reset 1 = software reset 0 = normal operation this bit is self - cleared after a 1 is written to it. rw/sc 0 0.14 loop b ack 1 = loopback mode 0 = normal operation rw 0 0.13 speed select 1 = 100mbps 0 = 10mbps this bit is ignored if auto - negotiation is enabled (register 0.12 = 1). rw set by the speed strapping pin. see the strapping options section for details. 0.12 auto- negotiation enable 1 = enable auto - negotiation process 0 = disable auto - negotiation process if enabled, the auto - negotiation result overrides the settings in register s 0.13 and 0.8. rw set by the nwayen strapping pin. see the strapping options section for details . 0.11 power - down 1 = power - down mode 0 = normal operation if software reset (register 0.15) is used to exit power -d own mode (register 0.11 = 1), two software reset writes (re gi ster 0.15 = 1) are required. the first write clears power -d own mode; the second write resets the chip and re - latches the pin strapping pin values. rw 0 0.10 isolate 1 = electrical isolation of phy from mii /rmii 0 = normal operation rw set by the iso strap ping pin. see the strapping options section for details . 0.9 restart auto - negotiation 1 = restart auto - negotiation process 0 = normal operation. this bit is self - cleared after a 1 is written to it. rw/sc 0 0.8 duplex mode 1 = full - duplex 0 = half - duplex rw the i nverse of the duplex strapping pin value. see the strapping options section for details . 0.7 collision test 1 = enable col test 0 = disable col test rw 0 0.6:0 reserved res erved ro 000_0000 register 1h C basic status 1.15 100base - t4 1 = t4 capable 0 = not t4 capable ro 0 1.14 100base - tx full - duplex 1 = capable of 100mbps full - duplex 0 = not capable of 100mbps full - duplex ro 1 1.13 100base - tx half - duplex 1 = capable of 100mbps half - duplex 0 = not capable of 100mbps half - duplex ro 1 1.12 10base - t full - duplex 1 = capable of 10mbps full - duplex 0 = not capable of 10mbps full - duplex ro 1 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 40 revision 1.0 address name description mode (1) default 1.11 10base - t half - duplex 1 = capable of 10mbps half - duplex 0 = not capable of 10mbps h alf - duplex ro 1 1.10:7 reserved reserved ro 000_0 1.6 no preamble 1 = preamble suppression 0 = normal preamble ro 1 1.5 auto- negotiation complete 1 = auto - negotiation process completed 0 = auto - negotiation process not completed ro 0 1.4 remote fault 1 = remote fault 0 = no remote fault ro/lh 0 1.3 auto- negotiation ability 1 = can perform auto - negotiation 0 = cannot perform auto - negotiation ro 1 1.2 link status 1 = link is up 0 = link is down ro/ll 0 1.1 jabber detect 1 = jabber detected 0 = jabber not detected (default is low) ro/lh 0 1.0 extended capability 1 = supports extended capability registers ro 1 register 2h C phy identifier 1 2.15:0 phy id number assigned to the 3rd through 18th bits of the organizatio nally unique identifier (oui). kendin communications oui is 0010a1 (hex) . ro 0022h register 3h C phy identifier 2 3.15:10 phy id number assigned to the 19th through 24th bits of the organizatio nally unique identifier (oui). kendin communications oui is 0010a1 (hex) . ro 0001_01 3.9:4 mode l number six- bit manufacturers model number ro 01_0110 3.3:0 revision number four - bit manufacturers revision number ro indicates silicon revision register 4h C auto - negotiation advertisement 4.15 next page 1 = next page capable 0 = no next page capabi lity rw 0 4.14 reserved reserved ro 0 4.13 remote fault 1 = remote fault supported 0 = no remote fault rw 0 4.12 reserved reserved ro 0 4.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and s ymmetric pause rw 00 4.9 100base - t4 1 = t4 capable 0 = no t4 capability ro 0 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 41 revision 1.0 address name description mode (1) default 4.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability rw set by the speed strapping pin. see the strapping options section for details . 4.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability rw set by the speed strapping pin. see the strapping options section for details . 4.6 10base - t ful l- duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - duplex capability rw 1 4.5 10base - t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability rw 1 4.4:0 selector field [00001] = ieee 802.3 rw 0_0001 register 5h C auto - negotiation link partner ability 5.15 next page 1 = next page capable 0 = no next page capability ro 0 5.14 acknowledge 1 = link code word received from partner 0 = link code word not yet received ro 0 5.13 remote fault 1 = remote fault detected 0 = no remote fault ro 0 5.12 reserved reserved ro 0 5.11:10 pause [00] = no pause [10] = asymmetric pause [01] = symmetric pause [11] = asymmetric and s ymmetric pause ro 00 5.9 100base - t4 1 = t4 capable 0 = no t4 capability ro 0 5.8 100base - tx full - duplex 1 = 100mbps full - duplex capable 0 = no 100mbps full - duplex capability ro 0 5.7 100base - tx half - duplex 1 = 100mbps half - duplex capable 0 = no 100mbps half - duplex capability ro 0 5.6 10base - t full - duplex 1 = 10mbps full - duplex capable 0 = no 10mbps full - du plex capability ro 0 5.5 10base - t half - duplex 1 = 10mbps half - duplex capable 0 = no 10mbps half - duplex capability ro 0 5.4:0 selector field [00001] = ieee 802.3 ro 0_0001 register 6h C auto - negotiation expansion 6.15:5 reserved reserved ro 0000_0000_000 6.4 parallel detection fault 1 = fault detected by parallel detection 0 = no fault detected by parallel detection ro/lh 0 6.3 link partner next page able 1 = link partner has next page capability 0 = link partner does not have next page capability ro 0 6.2 next page able 1 = local device has next page capability 0 = local device does not have next page capability ro 1 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 42 revision 1.0 address name description mode (1) default 6.1 page received 1 = new page received 0 = new page not received yet ro/lh 0 6.0 link partner auto- negotiation able 1 = link par tner has auto - negotiation capability 0 = link partner does not have auto - negotiation capability ro 0 register 7h C auto - negotiation next page 7.15 next page 1 = additional next pages will follow 0 = last page rw 0 7.14 reserved reserved ro 0 7.13 mess age page 1 = message page 0 = unformatted page rw 1 7.12 acknowledge2 1 = will comply with message 0 = cannot comply with message rw 0 7.11 toggle 1 = previous value of the transmitted link code word equaled logic 1 0 = logic 0 ro 0 7.10:0 message fiel d 11 - bit field to encode 2048 messages rw 000_0000_0001 register 8h C link partner next page ability 8.15 next page 1 = additional next pages will follow 0 = last page ro 0 8.14 acknowledge 1 = successful receipt of link word 0 = no successful receipt o f link word ro 0 8.13 message page 1 = message page 0 = unformatted page ro 0 8.12 acknowledge2 1 = can act on the information 0 = cannot act on the information ro 0 8.11 toggle 1 = previous value of transmitted link code word equal to logic 0 0 = pre vious value of transmitted link code word equal to logic 1 ro 0 8.10:0 message field 11 - bit field to encode 2048 messages ro 000_0000_0000 register 10h C digital reserved control 10.15:5 reserved reserved rw 0000_0000_000 10.4 pll o ff 1 = turn pll off automatically in edpd mode 0 = keep pll on in edpd mode. see also register 18h, bit [11] for edpd mode rw 0 10.3:0 reserved reserved rw 0000 register 11h C afe control 1 11.15:6 reserved reserved rw 0000_0000_00 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 43 revision 1.0 address name description mode (1) default 11.5 slow- oscillato r mode enable slow-o scillator mode is used to disconnect the input reference crystal/clock on the xi pin and select the on - chip slow oscillator when the ksz 8051mnlu / rnlu device is not in use after power - up. 1 = enable 0 = disable this bit au tomatically sets software power - down to the analog side when enabled. rw 0 11.4:0 reserved reserved rw 0_0000 register 15h C rxer counter 15.15:0 rxer counter receive error counter for symbol e rror frames ro/sc 0000h register 16h C operation mode strap override 16.15:11 reserved reserved rw 0000_0 16.10 reserved reserved ro 0 16.9 b-cast_off override 1 = override strap - in for b - cast_off if bit is 1, phy address 0 is non - broadcast. rw 0 16.8 reserved reserved rw 0 16.7 mii b - to -b override 1 = override strap - in for mii b ack - to -b ack mode (also set bit 0 of this register to 1) this bit applies only to ksz 8051mnlu . rw 0 16.6 rmii b - to -b override 1 = override strap - in for rmii back - to - back mode (also set bit 1 of this register to 1) this bit applies only to ksz 8051rnlu . rw 0 16.5 nand tree override 1 = override strap - in for nand tree mode rw 0 16.4:2 reserved reserved rw 0_00 16.1 rmii override 1 = override strap - in for rmii mode this bit applies only to ksz 8051rnlu . rw 0 16.0 mii override 1 = override strap - in for mii mode thi s bit applies only to ksz 8051mnlu . rw 1 register 17h C operation mode strap status 17.15:13 phyad[2:0] strap- in status [000] = strap to phy address 0 [001] = strap to phy address 1 [010] = strap to phy address 2 [011] = strap to phy address 3 [100] = str ap to phy address 4 [101] = strap to phy address 5 [110] = strap to phy address 6 [111] = strap to phy address 7 ro 17.12:10 reserved reserved ro 17.9 b-cast_off strap- in status 1 = strap to b -cast_off if bit is 1, phy address 0 is non - broadcast. ro 17.8 reserved reserved ro downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 44 revision 1.0 address name description mode (1) default 17.7 mii b - to -b strap- in status 1 = strap to mii back - to - back mode this bit applies only to ksz 8051mnlu . ro 17.6 rmii b - to -b strap- in status 1 = strap to rmii back - to - back mode this bit applies only to ksz 8051rnlu . ro 17.5 nand tree strap- in status 1 = strap to nand tree mode ro 17.4:2 reserved reserved ro 17.1 rmii strap - in status 1 = strap to rmii mode this bit applies only to ksz 8051rnlu . ro 17.0 mii strap - in status 1 = strap to mii mode this bit applies only to ks z 8051mnlu . ro register 18h C expanded control 18.15:12 reserved reserved rw 0000 18.11 edpd disabled energy - detect power - down mode 1 = disable 0 = enable see also register 10h, bit [4] for pll off. rw 1 18.10 100base - tx latency 1 = mii output is rando m latency 0 = mii output is fixed latency for both settings, all bytes of received preamble are passed to the mii output. this bit applies only to ksz 8051mnlu . rw 0 18.9:7 reserved reserved rw 00_0 18.6 10base - t preamble restore 1 = restore received preamble to mii output 0 = remove all seven bytes of preamble before sending frame (starting with sfd) to mii output this bit applies only to ksz 8051mnlu rw 0 18.5:0 reserved reserved rw 00_0000 register 1bh C interrupt control/status 1b.15 jabber interru pt enable 1 = enable jabber interrupt 0 = disable jabber interrupt rw 0 1b.14 receive error interrupt enable 1 = enable receive error interrupt 0 = disable receive error interrupt rw 0 1b.13 page received interrupt enable 1 = enable page received interru pt 0 = disable page received interrupt rw 0 1b.12 parallel detect fault interrupt enable 1 = enable parallel detect fault interrupt 0 = disable parallel detect fault interrupt rw 0 1b.11 link partner acknowledge interrupt enable 1 = enable link partner acknowledge interrupt 0 = disable link partner acknowledge interrupt rw 0 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 45 revision 1.0 address name description mode (1) default 1b.10 link - down interrupt enable 1= enable link - down interrupt 0 = disable link - down interrupt rw 0 1b.9 remote fault interrupt enable 1 = enable remote fault interrupt 0 = disable remote fault interrupt rw 0 1b.8 link - up interrupt enable 1 = enable link - up interrupt 0 = disable link - up interrupt rw 0 1b.7 jabber interrupt 1 = jabber occurred 0 = jabber did not occur ro/sc 0 1b.6 receive error interrupt 1 = receive error occurred 0 = receive error did not occur ro/sc 0 1b.5 page receive interrupt 1 = page receive occurred 0 = page receive did not occur ro/sc 0 1b.4 parallel detect fault interrupt 1 = parallel detect fault occurred 0 = parallel detect fault did not occur ro/sc 0 1b.3 link partner acknowledge interrupt 1 = link partner acknowledge occurred 0 = link partner acknowledge did not occur ro/sc 0 1b.2 link - down interrupt 1 = link - down occurred 0 = link - down did not occur ro/sc 0 1b.1 remote fault interrupt 1 = remote fault occurred 0 = remote fault did not occur ro/sc 0 1b.0 link - up interrupt 1 = link - up occurred 0 = link - up did not occur ro/sc 0 register 1dh C linkmd control/status 1d.15 cable diagnostic test enable 1 = enable cable diagnostic test. after test has completed, this bit is self - cleared. 0 = indicates cable diagnostic test (if enabled) has completed and the status information is valid for read. rw/sc 0 1d.14:13 cable diagnostic test result [00] = normal condition [01] = open condition has been detect ed in cable [10] = short condition has been detected in cable [11] = cable diagnostic test has failed ro 00 1d.12 short cable indicator 1 = short cable (<10 meter) has been detected by linkmd ro 0 1d.11:9 reserved reserved rw 000 1d.8:0 cable fault c ounter distance to fault ro 0_0000_0000 register 1eh C phy control 1 1e.15:10 reserved reserved ro 0000_00 1e.9 enable pause (flow control) 1 = flow control capable 0 = no flow control capability ro 0 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 46 revision 1.0 address name description mode (1) default 1e.8 link status 1 = link is up 0 = link is down ro 0 1e.7 polarity status 1 = polarity is reversed 0 = polarity is not reversed ro 1e.6 reserved reserved ro 0 1e.5 mdi/mdi - x state 1 = mdi -x 0 = mdi ro 1e.4 energy detect 1 = signal present on receive differential pair 0 = no signal detected on receive differential pair ro 0 1e.3 phy isolate 1 = phy in isolate mode 0 = phy in normal operation rw 0 1e.2:0 operation mode indication [000] = still in auto - negotiation [001] = 10base - t half - duplex [010] = 100base - tx half - duplex [011] = reserved [100] = r eserved [101] = 10base - t full - duplex [110] = 100base - tx full - duplex [111] = reserved ro 000 register 1fh C phy control 2 1f.15 hp_mdix 1 = hp auto mdi/mdi - x mode 0 = micrel auto mdi/mdi - x mode rw 1 1f.14 mdi/mdi - x select when auto mdi/mdi - x is disabled, 1 = mdi - x mode transmit on rxp,rxm (pins 5 , 4 ) and receive on txp,txm (pins 7 , 6) 0 = mdi mode transmit on txp,txm (pins 7 , 6 ) and receive on rxp,rxm (pins 5 , 4) rw 0 1f.13 pair swap disable 1 = disable auto mdi/mdi -x 0 = enable auto mdi/mdi -x rw 0 1 f.12 reserved reserved rw 0 1f.11 force link 1 = force link pass 0 = normal link operation this bit bypasses the control logic and allows the transmitter to send a pattern even if there is no link. rw 0 1f.10 power saving 1 = enable power saving 0 = dis able power saving rw 0 1f.9 interrupt level 1 = interrupt pin active high 0 = interrupt pin active low rw 0 1f.8 enable jabber 1 = enable jabber counter 0 = disable jabber counter rw 1 downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 47 revision 1.0 address name description mode (1) default 1f.7 rmii reference clock select 1 = rmii 50mhz clock mode; clock input to xi (pin 9) is 50mhz 0 = rmii 25mhz clock mode; clock input to xi (pin 9) is 25mhz this bit applies only to ksz 8051rnlu . rw 0 1f.6 reserved reserved rw 0 1f.5:4 led mode [00] = led1: speed led0: link/activity [01] = led1: activity led0: link [10], [11] = reserved rw 00 1f.3 disable transmitter 1 = disable transmitter 0 = enable transmitter rw 0 1f.2 remote loopback 1 = remote (analog) loopback is enabled 0 = normal mode rw 0 1f.1 enable sqe test 1 = enable sqe test 0 = disable sqe test rw 0 1f.0 disable data scrambling 1 = disable scrambler 0 = enable scrambler rw 0 note: 1. rw = read/write. ro = read only. sc = self - cleared. lh = latch high. ll = latch low. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 48 revision 1.0 absolute maximum ratings (1) supply voltage (v in ) (v dd_1.2 ) .................................................. ? 0.5v to +1.8v (v ddio, v dda_3.3 ) ....................................... ? 0.5v to +5.0v input voltage (all inputs) .............................. ? 0.5v to +5.0v output voltage (all outputs) ......................... ? 0.5v to +5.0v lead temperature (soldering, 10sec.) ....................... 260c storage temperature (t s ) ......................... C 55c to +150c operating ratings (2) supply voltage (v ddio_3.3, v dda_3.3 ) .......................... +3.135v to +3.465v (v ddio_2.5 ) ........................................ +2.375v to +2.625v (v ddio_1.8 ) ........................................ +1.710v to +1.890v ambient temperature (t a , automotive qualified ) .................... C 40c to +85c maximum junction temperature (t j max.) ................ 125c thermal resistance ( ja ) ......................................... 34 c/w thermal resistance ( jc ) ........................................... 6 c/w electrical characteristics (3) symbol parameter condition min . typ . max . units supply current (v ddio , v dda_3.3 = 3.3v) (4) i dd1_3.3v 10base -t full - duplex traffic @ 100% utilization 41 ma i dd2_3.3v 100base - tx full - duplex traffic @ 100% utilization 47 ma i dd3_3.3v edpd mode ethernet cable disconnected (reg. 18h.11 = 0) 20 ma i dd4_3.3v power - down mode software power - down (reg. 0h.11 = 1) 4 ma cmos level inputs v ih input high voltage v ddio = 3.3v 2.0 v v ddio = 2.5v 1.8 v v ddio = 1.8v 1.3 v v il input low voltage v ddio = 3.3v 0.8 v v ddio = 2.5v 0.7 v v ddio = 1.8v 0.5 v |i in | input current v in = gnd ~ vddio 10 a cmos level outputs v oh output high voltage v ddio = 3.3v 2.4 v v ddio = 2.5v 2.0 v v ddio = 1.8v 1.5 v v ol output low voltage v ddio = 3.3v 0.4 v v ddio = 2.5v 0.4 v v ddio = 1.8v 0.3 v |i oz | output tri - state leakage 10 a led output i led output drive current each led pin (led0, led1) 8 ma n otes: 1. exceeding the absolute maximum rating can damage the device. stresses greater than the absolute maximum rating can cause perm anent damage to the device. operation of the device at these or any other conditions above those specified in the operating s ections of this specification is not implied. maximum conditions for extended periods may affect reliabil ity. 2. the device is not guaranteed to function outside its operating rating. 3. t a = 25c. specification is for packaged product only. 4. current consumption is for the single 3.3v supply ksz 8051mnlu / rnlu device only, and includes the transmit driver current and the 1.2v supply voltage (v dd_1.2 ) that are supplied by the ksz 8051mnlu / rnlu . downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 49 revision 1.0 symbol parameter condition min . typ . max . units all pull - up/pull - down pins (including strapping pins) pu internal pull -u p resistance v ddio = 3.3v 30 45 73 k v ddio = 2.5v 39 61 102 k v ddio = 1.8v 48 99 178 k pd internal pull - down resistance v ddio = 3.3v 26 43 79 k v ddio = 2.5v 34 59 113 k v ddio = 1.8v 53 99 200 k 100base - tx transmit (measured differentially after 1:1 transformer) v o peak differential output voltage 100 termination across differential output 0.95 1.05 v v imb output voltage imbalance 100 termination across differential output 2 % t r , t f rise/fall time 3 5 ns rise/fall time imbala nce 0 0.5 ns duty cycle distortion 0.25 ns overshoot 5 % output jitter peak - to - peak 0.7 ns 10base - t transmit (measured differentially after 1:1 transformer) v p peak differential output voltage 100 termination across differential output 2.2 2.8 v jitter added peak - to - peak 3.5 ns t r , t f rise/fall time 25 ns 10base - t receive v sq squelch threshold 5mhz square wave 400 mv transmitter C drive setting v set reference voltage of i set r(i set ) = 6.49 k 0.65 v ref_clk output 50mh z rmii clock output jitter peak - to - peak (applies only to ksz 8051rnlu in rmii C 25 mhz clock mode ) 300 ps 100mbps mode C industrial applications parameters clock phase delay C xi input to mii txc output xi (25mhz clock input) to mii txc (25mhz clock out put) delay, referenced to rising edges of both clocks. (applies only to ksz 8051mnlu in mii mode) 15 20 25 ns t llr link loss reaction (indication) time link loss detected at receive differential inputs to phy signal indication time for each of the followin g: 1. for led mode 00, speed led output changes from low (100mbps) to high (10mbps, default state for link - down). 2. for led mode 01, link led output changes from low (link - up) to high (link - down). 3. intrp pin asserts for link - down status change. 4.4 s downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 50 revision 1.0 timing diagrams mii sqe timing (10base - t) figure 11 . mii sqe timing (10base - t) timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t sqe col (sqe) delay after txen de - asserted 2.2 s t sqep col (sqe) pulse duration 1.0 s table 13 . mii sqe timing (10base - t) parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 51 revision 1.0 mii transmit timing (10base - t) figure 12 . mii tran smit timing (10base - t) timing parameter description min. typ. max. unit t p txc period 400 ns t wl txc pulse width low 200 ns t wh txc pulse width high 200 ns t su1 txd[3:0] setup to rising edge of txc 120 ns t su2 txen setup to rising edge of t xc 120 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 600 ns t crs2 txen low to crs de - asserted latency 1.0 s table 14 . mii tra nsmit timing (10base - t) parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 52 revision 1.0 mii receive timing (10base - t) figure 13 . mii receive timing (10base - t) timing parameter description min. typ. max. unit t p rxc period 400 ns t wl rxc pulse width low 200 ns t wh rx c pulse width high 200 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 205 ns t rlat crs to (rxdv, rxd[3:0]) latency 7.2 s table 15 . mii receive timing (10base - t) parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 53 revision 1.0 mii transmit timing (100b ase - tx) figure 14 . mii transmit timing (100base -tx) timing parameter description min. typ. max. unit t p txc period 40 ns t wl txc pulse width low 20 ns t wh txc pulse width high 20 ns t su1 txd[3:0] setup to rising e dge of txc 10 ns t su2 txen setup to rising edge of txc 10 ns t hd1 txd[3:0] hold from rising edge of txc 0 ns t hd2 txen hold from rising edge of txc 0 ns t crs1 txen high to crs asserted latency 72 ns t crs2 txen low to crs de - asserted latency 72 ns table 16 . mii transmit timing (100base - tx) parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 54 revision 1.0 mii receive timing (100base - tx) figure 15 . mii receive timing (100base -tx) timing parameter description min. typ. max. unit t p rx c period 40 ns t wl rxc pulse width low 20 ns t wh rxc pulse width high 20 ns t od (rxdv, rxd[3:0], rxer) output delay from rising edge of rxc 25 ns t rlat crs to (rxdv, rxd[3:0] ) latency 170 ns table 17 . mii receive ti ming (100base - tx) parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 55 revision 1.0 rmii timing figure 16 . rmii timing C data received from rmii figure 17 . rmii timing C data input to rmii timing parameter description min. typ. max. unit t cyc c lock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 7 10 13 ns table 18 . rmii timing parameters C ksz 8051rnlu (25mhz input to xi pin, 50mhz output from ref_clk pin) timing parameter description min. typ. max. unit t cyc clock cycle 20 ns t 1 setup time 4 ns t 2 hold time 2 ns t od output delay 8 11 13 ns table 19 . rmii timing parameters C ksz 8051rnlu (50mhz input to xi pin) downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 56 revision 1.0 auto - negotiation timing figure 18 . auto - negotiation fast link pulse (flp) timing timing parameter description min. typ. max. units t btb flp b urst to flp burst 8 16 24 ms t flpw flp b urst width 2 ms t pw clock/data p ulse width 100 ns t ctd clock p ulse to d ata p ul se 55.5 64 69.5 s t ctc clock pulse to c lock p ulse 111 128 139 s number of clock/d ata p ulse s per flp b urst 17 33 table 20 . auto - negotiation fast link pulse (flp) timing parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 57 revision 1.0 mdc/mdio timing figure 19 . mdc/mdio timing timing parameter description min. typ. max. unit t p mdc period 400 ns t md1 mdio (phy input) setup to rising edge of mdc 10 ns t md2 mdio (phy input) hold from rising edge of mdc 4 ns t md3 mdio (phy output) delay from rising edge of mdc 5 ns table 21 . mdc/mdio timing parameters downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 58 revision 1.0 power -u p/ r eset timing the ksz 8051mnlu / rnlu reset timing requirement is summarized in figure 20 and table 22 . figure 20 . power -u p/reset timing parameter description min. max. units t vr supply voltage (v ddio, v dda_3.3 ) rise time 300 s t sr stable supply voltage (v ddio, v dda_3.3 ) to reset high 10 ms t cs configuration setup time 5 ns t ch configuration hold time 5 ns t rc reset to strap - in pin output 6 ns table 22 . power -u p/reset timing parameters the supply voltage ( v ddio and v dda_3.3 ) power - up waveform should be monotonic . t he 300 s minimum rise time is from 10% to 90%. for warm reset, the reset (rst#) pin should be asserted low for a minimu m of 500 s. the strap - in pin values are read and updated at the de - assertion of reset. after the de - assertion of reset, wait a minimum of 100 s before starting programming on the miim (mdc/mdio) i nterface. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 59 revision 1.0 reset circuit figure 21 shows a reset circuit recommended for powering up the ksz 8051mnlu / rnlu if reset is triggered by the power supply. figure 21 . recommended reset circuit figure 22 shows a reset circuit recommended for applications where reset is driven by anoth er device (for example , the cpu or an fpga). at power - on - reset, r, c , and d1 provide the necessary ramp rise time to reset the ksz 8051mnlu / rnlu device. the rst_out_ n from the cpu/fpga prov ides the warm reset after power - up. figure 22 . recommended reset circuit for i nterf acing with cpu/fpga reset output downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 60 revision 1.0 reference circuits C led strap-in pins the pull - up, float , and pull - down reference circuits for the led1/speed and led0/nwayen strapping pins are shown in figure 23 for 3.3v and 2.5v vddio. figure 23 . reference circuits for led strapping pins for 1.8v vddio, led indication support is not recommended due to the low voltage. without the led i ndicator, the speed and nwayen strapping pins are functional with a 4.7 k p ull - up to 1.8v vddio or float for a value of 1, and with a 1.0 k pull - down to ground for a value of 0. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 61 revision 1.0 reference clock C connection and selection a crystal or external clock source, such as an oscillator, is used to provide the referenc e clock for the ksz 8051mnlu / rnlu . for the ksz 8051mnlu in all operating modes and for the ksz 8051rnlu in rmii C 25mhz clock mode, the reference clock is 25 mhz. the reference clock connections to xi (pin 9) and xo (pin 8 ), and the reference clock selection criteria , are provided in figure 24 and table 23 . figure 24 . 25mhz crystal/oscillator reference clock connection characteristics value unit s frequency 25 mhz frequency tolerance (max .) 50 ppm table 23 . 25mhz crystal / reference clock selection criteria for the ksz 8051rnlu in rmii C 50mhz clock mode, the reference clock is 50mhz. the reference clock connections to xi (pin 9), and the reference clock selection criteria are provided in figure 25 and table 24 . figure 25 . 50mhz oscillator reference clock connection characteristics value units frequency 50 mhz frequency tolerance (max) 50 ppm table 24 . 50mhz oscillator / reference clock selection criteria downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 62 revision 1.0 magnetics C connection and selection a 1:1 isolation transformer is required at the line interface. use one with integrated com mon - mode chokes for designs exceeding fcc requirements. the ksz 8051mnlu / rnlu design incorporates voltage - mode transmit drivers and on - chip terminations. with the voltage - mode implementation, the transmit drivers supply the common - mode voltages to the two differential pairs. therefore, the two transformer center tap pins on the ksz 8051mnlu / rnlu side should not be connected to any power supply source on the board ; instead , the center tap pins should be separated from one another and connected through separate 0.1 f common - mode capacitors to ground. separation is required because the common - mode voltage is different between transmitting and receiving differential pairs . figure 26 shows the typical magnetic interface circuit for the ksz 8051mnlu / rnlu . figure 26 . typical magnetic interface circuit downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 63 revision 1.0 table 25 lists recommended magnetic characte ristics. parameter value test condition turns ratio 1 ct : 1 ct open - circuit inductance (min.) 350 h 100mv, 100khz, 8ma insertion loss ( typ .) C 1. 1 db 10 0k hz to 100mhz hipot (min.) 1500vrms table 25 . magnetics selection criteria table 26 is a list of compatible single - port magnetics with separated transformer center tap pins on the phy chip side that can be used with the ksz 8051mnlu / rnlu . manufacturer par t number temperature range magnetic + rj - 45 bel fuse s558 - 5999 - u7 0c to 70c no bel fuse si- 46001 -f 0c to 70c yes bel fuse si- 50170 -f 0c to 70c yes delta lf8505 0c to 70c no halo hfj11 - 2450e 0c to 70c yes halo tg110 - e055n5 C 40c to 85c no lankom lf - h41s -1 0c to 70c no pulse h1102 0c to 70c no pulse h1260 0c to 70c no pulse hx1188 C 40c to 85c no pulse j00 - 0014 0c to 70c yes pulse jx0011d21nl C 40c to 85c yes tdk tla - 6t718a 0c to 70c yes transpower hb726 0c to 70c no wu rth/midcom 000 - 7090 - 37r - lf1 C 40c to 85c no table 26 . compatible single -p ort 10/100 magnetics downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 64 revision 1.0 recommended land pattern figure 27 . recommended land pattern, 32 - pin (5mm x 5mm) qfn red circles in dicate thermal vias. they should be 0.350mm in diameter and be connected to the gnd plane for maximum thermal performance. green rectangles (with shaded area) indicate solder stencil openings on the exposed pad area. they should be 0.87 x 0.87 mm in size, 1 . 07 mm pitch. downloaded from: http:///
micrel , inc. ksz8051mnlu/ ksz 8051rnlu february 1 7, 2013 65 revision 1.0 package information (1) 32 - pin (5mm x 5mm) qfn note: 1. package information is correct as of the publication date. for updates and most current infor mation, go to www.m icrel.com . micrel, inc. 2180 fortune drive san jose, ca 95131 usa tel +1 (408) 944 - 0800 fax +1 (408) 474 - 1000 web http://www.micrel.com micrel makes no representations or warranties with respect to the accuracy or completeness of the information fur nished in this data sheet. this information is not intended as a warranty and micrel does not assume responsibility for its use. micrel reserves the right to change circuitry, specifications and descriptions at any time without notice. no license, whether express, implied, arising by estoppel or otherwise, to any intellectual property rights is granted by this document. except as provided in micrels terms and conditions of sale for such products, mic rel assumes no liability whatsoever, and micrel disclaims any express or implied warranty relating to the sale and/ or use of micrel products including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pat ent, copyright or other intellectual property right . micrel products are not designed or authorized for use as components in life support appl iances, devices or systems where malfunction of a product can reasonably be expe cted to result in personal injury. life support devices or systems are devices or syste ms that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to res ult in a significant injury to the user. a purchasers use or sale of micrel products for use in life support appliances, devices or systems is a purchasers own risk a nd purchaser agrees to fully indemnify micrel for any damages resulting from such use or sale. ? 2013 micrel, incorporated. downloaded from: http:///

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